Friday, May 6, 2016

Plunify 2016 - H1 Newsletter

In this edition we have some exciting updates about our new office in East Singapore, new Sales Reps onboard, an exciting investment announcement and last but not least, the upcoming release of InTime version 1.4.4.

Plunify opens new headquarters in eastern Singapore
Plunify appoints new reps in Beijing and Israel
New InTime software version 1.4.4 released
InTime now supports latest Vivado version 2016.1
Plunify closese funding to enhance FPGA design timing closure capabilities
Free InTime evaluation and hands-on training

Plunify opens new headquarters in eastern Singapore

From our western origin, we crossed the island and set up base in the Aljunied area of Singapore. Now we are in a brand new building, "Atrix", with a cosy loft and a facility to beat the heat in the form of a swimming pool. We are also making arrangements for a training facility where you can come and experience the inTime software and get your hands dirty working on various timing closure problems.

Part of our expansion plans includes opening new RnD offices in Kuala Lumpur, Chengdu and Nanjing. We are hiring engineers and sales staff in all these areas.

If you are in Singapore and fancy a dip in our new, cool swimming pool, let us know! Only if you promise to bring the drinks!

Plunify appoints new sales representatives in Beijing and Israel

We would like to welcome new sales representative, the Satris Group, in Israel. Satris is a leading distributor of EDA products in Israel, providing sales, marketing and technical support services for the products it represents. It was set up by a group of EDA veterans with deep knowledge of the Israeli market, its customers and its needs. Satris’ team is well known for its high level of technical expertise and also offers advanced design and verification services, providing Israeli customers with a full, high quality solution. 

Not far from home, we would also like to welcome onboard our new partner in Beijing China, Beijing Hontak Technology. They were excited to take Plunify to their customers given the unique value proposition which only Plunify can offer to FPGA designers.

New InTime software version 1.4.4 released

In the latest version of the InTime software version 1.4.4, we have added further optimizations in the "Extra Opt Exploration" recipe. If you hit a roadblock running the default InTime recipe to get better timing results, try this new recipe that uses additional non-project flows recommended by Vivado. Some of these additional timing closure optimizations include:

  • High-fanout Optimization (Default)
  • Placement-Based Optimization (Default)
  • Rewire 
  • Critical-cell Optimization
  • DSP Register Optimization 
Xilinx user guide 904 gives a good idea about the available options for running the iterative flows. InTime uses these flows as part of its machine learning algorithm to achieve timing closure, allowing users to take advantage of non-standard Vivado flows alongside the machine learning capabilities of InTime. "We believe this option will result in significant improvement in the timing performance with very complex designs meeting the timing requirements," says Harnhua Ng, VP of Engineering. 

InTime supports latest Vivado version 2016.1

InTime now supports the latest update from Xilinx Vivado software version 2016.1. We added the support for the new Ultrascale devices for both Kintex and Zynq devices. As 2016.1 is relatively new, we are working on comparing this version with the older 2015.4. Watch out for our report!

Plunify Closes Funding Round to Enhance FPGA Design Timing Closure Capabilities
The investment will be used to scale Plunify’s sales and technical support channels, as well as extend its marketing reach to promote its InTime software and educate FPGA design companies on how to use InTime to solve design problems and speed up their products’ Time to Market.

Read the complete funding announcement here.

Free evaluation and hands on training
To get your hands on the InTime software and free hands-on training, just drop us an email at We will get in touch with you shortly after. You can also visit our office to try out some of the existing designs to see how Plunify helps to close timing issues in different designs on both Altera and Xilinx FPGAs. 

Wednesday, October 7, 2015

"A Brief History of InTime" - Overview of past projects

An evaluation customer made an interesting comment recently.

Due to the rigorous nature of InTime's approach, we'd often get comments like, "You mean this takes 100 compilations more than usual?!" This time it was, "I need to evaluate InTime more as it met timing too quickly." It felt like a compliment hidden within a complaint, or vice versa! We're just happy that they put in the time and effort to evaluate InTime and it gave them good results.

I actually think that the two pieces of feedback mean the same thing -- that there is a lack of understanding the software, not so much in terms of how it works, but in realizing how much potential this approach has. As engineers and innovators, we take a lot of pride in creation. Most of the time, competent FPGA designers come with a whole bag of techniques and tricks in their repertoire. They can solve most problems using their understanding of the RTL and architecture.  As one partner puts it "We felt like we'd lost if we started working with the settings (of the FPGA tools)." It was almost as if any approach not involving RTL changes bordered on cheating.

It is not cheating! Like it or not, you are already using default values for the settings in every design whether you realize it or not; it's just that when your design doesn't meet timing or doesn't fit into the target device, the defaults have not helped. The question to ask then, is how much can the settings help in your particular design?

Can InTime's approach really solve the problems you are seeing? It is true that using the optimal group of settings might not enable you to hit that performance target. However, it is undeniable that using the right ones right from the start will get you more quickly to a better result. Let us look at various customer designs and their results using InTime below:

The full details can be found at this URL.

The various charts show three different metrics, TNS, WS(Worst Slack) and Area, across various customer designs -- color-coded to differentiate between customers. We highlight the left-most cell in green if there is at least 80% improvement over the original score, whether it is TNS, WS or Area. 100% improvement means we have met timing. Grey indicates less than 80% improvement and red is less than 50% improvement. N.A means that the original timing scores are not captured in the dataset.

Here is what was observed for successful cases:

1. Planning and Coding Guidelines

If you plan carefully and practice FPGA-optimized coding guidelines, it is easy to get InTime to produce the results. (One of the cases in red is due to asynchronous design issues. The other did too few compilation runs.) Xilinx has published detailed coding guidelines to help in this area.

2. Starting Timing Scores
This might seem obvious but a higher initial TNS score makes it harder to close timing than a lower one! From our data, the average cutoff TNS is -6000ns. Anything below -6000ns is possible in general. So far InTime has not closed timing on designs with initial TNS values that are worse than -6000ns. If your design is still beyond this threshold, for example, at an earlier stage of the design flow, InTime is still helpful because it points out significant critical paths that you should tackle first. For the record, the "worst" TNS we've encountered was a whopping -60,000ns!

Although we don't have sufficient data to justify some observations, there are some other interesting snippets of note. For instance, a bit of floorplanning seems helpful -- in general, a post-floorplanned design converges faster (fewer number of compilations required, more successful results). Also, there are definitely correlations between using older and newer FPGA tool versions.

One last thing to mention here: The charts and analytics are made possible by a collective crowd-sourced effort from our customers and partners. By sharing InTime data with us, they help further improve our analytics. If you are planning to evaluate InTime in future, please help by sharing with us your InTime data.

Let us know if you have any questions. Thanks for reading!

Wednesday, April 22, 2015

Cool stuff! DIY FPGA-based HDMI ambient lighting

Once in a while we come across cool stuff like this! Have fun!

Check them out: Zero Characters Left: DIY FPGA-based HDMI ambient lighting

"Ambient lighting is a technique that creates light effects around the television that correspond to the video content. It has been pioneered by Philips under the brand Ambilight. In this project we will create a basic FPGA-based ambient lighting system that reads the video signal over HDMI. This means we are not limited to computer output. We can use it together with DVD players, video game consoles, etc."