Friday, July 22, 2016

Thank you, Mark

I think that most of us have experienced times when we were steadily going about our lives, absorbed in our daily routines and tasks, often content in the knowledge that whatever it was, we were making steady progress on all fronts; and then life suddenly throws a curveball.

Imagine a person whom you regard as an mentor and a role model, someone whom you have the utmost respect and admiration for. You may not see or hear from him everyday, but you catch up regularly and always come away with new insights and a sense of assurance that you can never go wrong by heeding his advice. During trying times, this person's actions and demeanour alone restores faith in the world.

Now, imagine if that person is suddenly called away, never to return.

On this day, with the dawn came terrible news in the form of an email and a phone call. Mark Templeton, a person very dear to everyone at Plunify, is no longer with us. The same Mark, with whom Kirvy and I had spoken just a week or two ago, with whom we had eagerly made plans to meet in person next month despite normally being on different sides of the Pacific.

The first time Kirvy and I met Mark was when we were looking for seed funding for Plunify. Us being a no-name startup from Singapore, it seemed perfectly logical that someone of Mark's stature would exchange a few pleasantries and send us on our way. Of course that was not the case -- we were struck by his openness and willingness to listen; one thing led to another, and about a year and a half later, Mark became an investor and mentor not only to Plunify but to Kirvy and me. He always made himself available for questions and advice, and never hesitated to offer his help.

He is, in a nutshell, everything that I aspire to be -- a brilliant engineer, a successful entrepreneur, a passionate contributor to our community, and a family man. The generosity of spirit and faith he bestowed upon us from day one was frankly, astonishing and gave us strength on many a day when things got hairy. Simply put, Mark is one of the nicest people whom Kirvy and I have had the honor and pleasure of knowing.

One of my fondest memories of Mark was when I arrived at the office one morning to find him perched on a ladder, upper body halfway into the false ceiling, installing LAN cables for the office. The sight of an industry giant who could have summoned throngs of people to do what he was doing, but who chose instead to do it himself, was and still is, to me, the very embodiment of a true engineer. I asked him why he did it, and Mark simply shrugged and said, "Because I can." It is one of those moments that I will cherish forever.

To Mark: Thank you from the bottom of our hearts. There is so much we want to say. You left an indelible impression on us. We will always be inspired by your words and deeds, and strive to be the company and human beings that you believed we can become.

Tuesday, June 14, 2016

Mythbuster: Is InTime with Vivado 2016.1 better than the previous version?

Oh! The paint hasn't dried on my Vivado 2016.1 blogpost and 2016.2 is already out!

The early months of 2016 saw the release of Vivado 2016.1. We naturally assumed that it would be better than the previous version, given what we heard from beta users and developers.

In many cases, users usually base their opinions on results from a single design; for example, Vivado 2015.x gives you N ns of Total Negative Slack (TNS) or Worst Slack (WS). If Vivado 2016.1 gives you a better result, the newer version performs better, otherwise it is worse. This is about the average amount of patience a typical user can muster to form an opinion, since the overriding concerns are more about finishing projects rather than evaluating the tools.

Sunday, June 5, 2016

A Sum of Part(ition)s

Altera FPGA users need no introduction to Partition Merge, a step in the Altera Quartus-II ("Quartus") design compilation process that combines multiple netlists (post-synthesis or post-fit) into a single, complete netlist. Quartus triggers this step automatically whenever it detects any design partitions in a project.

Will Quartus always run Partition Merge? If not, why?
Quartus tries to detect partitions in your design and only runs Partition Merge if there is at least one partition.

For example, if you import a Quartus Exported Partition File (.qxp file) into your project and designate it as a partition, Quartus will run Partition Merge during the compilation process.
However, if you simply import the same .qxp netlist as a source file but neglect to designate it as a partition, Quartus will NOT run Partition Merge automatically.

Okay, so what?
Working with a customer, we found that timing results improved significantly (see Table 1 below) when Partition Merge was run versus when it was not run.

Arria 10 design Without Partition Merge
(.qxp as source file)
With Partition Merge
(same .qxp as a partition)
Total Negative Slack (TNS)
-1533.727 ns
-387.006 ns
Worst Slack (Setup / Hold)
-0.807 ns
-0.516 ns
Table 1: Timing results with and without Partition Merge

Intuitively, the above results seem logical because Partition Merge performs optimizations such as resource sharing, thus affecting timing performance. The "gotcha" here is that one might think that importing a netlist automatically triggers Partition Merge, but no -- you would have to explicitly declare it as a partition before things work as expected.

How we found this 'bug' was actually rather interesting -- InTime exported a result for a customer and the customer proceeded to reproduce the same result in Quartus, but obtained a much worse result (exactly what you see in Table 1 above). After banging our heads against the wall for a couple of days, we finally found the cause of the differences and am documenting it here in case someone else runs into a similar predicament.

At the end of the day, what matters is that you should be getting the best timing performance that your FPGA tool can produce, with minimal fuss.