Tuesday, February 10, 2015

Focus on Worst Slack or Total Negative Slack? This chart may have the answer.

One of the questions that FPGA designers wonder and sometimes even argue about, is: Should the implementation tools focus on Worst Slack (WS) or Total Negative Slack (TNS)?

FPGA tools typically devote more attention to WS, but there are tradeoffs. If WS is small yet many paths fail timing, then TNS can be huge. Similarly, if TNS is slight but WS is failing by a lot, that is also a problem.

To answer this question, we added a feature to collate the data for both timing values and ran about 1000 compilations on a small design (Cyclone V, about 9% utilization) using different synthesis and fitter settings.

This is what we see. The default result is marked by the black dot. The Y-axis represents the absolute value of the TNS and the X-axis, the absolute value of failing WS.

The chart is divided into 4 quadrants, green means these compilations give better TNS and WS compared to the original design.

Besides looking like a pretty smattering of colored dots, we can see that the TNS flattens out when it is closer to zero but the worst slack still keeps improving.

Taking a closer look,

What do you think?
Make your own conclusions, and please share your thoughts with us!

Monday, February 9, 2015

From Chip Design: The Coming Year in EDA: What Will Shape 2015


Hamhua Ng, CEO of Plunify said: “There is much truth in the saying, ‘Those who don’t learn from history are doomed to repeat it,’ especially in the data-driven world that we live in today. It seems like every retailer, social network and financial institution is analyzing and finding patterns in the data that we generate. To businesses, being able to pick out trends from consumer behavior and quickly adapt products and services to better address customer requirements will result in significant cost savings and quality improvements.

Sunday, January 11, 2015